The processor’s instruction sheet

Here is the processor row from StarFive's VisionFive 2 product brief: a JH-7110, four CPU cores plus a monitor core, an RV64GC ISA, a clock up to 1.5 GHz, 2 MB of L2 cache. Quick question before you buy the board — which of those six facts says what your binary may contain, and which say how long it will take to run?

Board:      VisionFive 2Processor:  StarFive JH-7110CPU:        RISC-V quad-core plus monitor coreISA:        RV64GCClock:      up to 1.5 GHzL2 cache:   2 MB

The brief prints them in one row as if they were the same kind of fact, and they are not even close. RV64GC is a contract about vocabulary — which instructions exist and what they mean. The JH-7110 is one particular machine that signed the contract, and every performance-shaped number in the row belongs to it, never to the four letters.

Decode the letters#

The letters reward decoding, and the official naming convention is short: a base, then extensions. G is shorthand for the general-purpose collection IMAFDZicsr_Zifencei, and C adds compressed encodings.

What the letters actually decide is whether a binary's instructions belong to this machine's vocabulary. Compile something that assumes the vector extension and this board will refuse you — the listing says GC, and no amount of 64-bitness smuggles a V in.

Take C, the extension that sounds most like a feature. It changes encodings, letting common operations use 16-bit instruction words beside the base 32-bit ones, which can shrink code — whether that speeds anything up depends on this chip's fetch and decode, which the letter says nothing about. The letter buys compatibility.

G is the same shape of promise, wider: integer multiplication, atomics, both floating-point widths, control-register access, instruction-fetch fencing. A compiler learns those words exist together on this target. How fast the JH-7110 pronounces them appears nowhere in the name.

One sheet, many machines#

Nothing in those letters belongs to StarFive. RISC-V International publishes the instruction sheet and deliberately stops there — the standards body describes the ISA as a protocol between software and hardware, and a core implementing it may be open source or entirely proprietary. The open part is the contract, the way USB is open while the controllers inside remain somebody's trade secret.

An alphabet this flexible cuts both ways, because a Linux distribution cannot negotiate letters with every board it might boot on. Profiles exist for exactly that: RVA23 bundles the extensions an application processor must supply together — the vector extension finally among the mandatory ones — so a distribution targets one profile name and the letter arithmetic becomes the vendor's problem.

See the contract at one call boundary#

The contract is easiest to respect when you watch it work at a single call boundary. Two arguments in, one addition, one return:

long add_two(long a, long b) {    return a + b;}

add_two:    add a0, a0, a1    ret

The procedure-call ABI puts the first two integer arguments in a0 and a1 and the return value back in a0, so add a0, a0, a1 followed by ret is the whole function. Your compiler may emit something slightly different, but separately compiled code has to share this register agreement or nothing links.

Everything else is left to whoever builds the core: in-order or out-of-order pipeline, cache sizes, execution width, fabrication process, power budget. Two processors can run this exact binary and take wildly different amounts of time, and both are keeping the contract.

Even the row's honest performance facts — four cores, 1.5 GHz — leave your question unfinished. A single-threaded parser probably cares more about branch prediction and memory latency than about the three cores it leaves idle, and "up to 1.5 GHz" is a ceiling, not a measurement of anything.

StarFive's fuller board specification adds detail beside the ISA, and it still does not disclose enough to predict your workload. So the purchase decision ends where it always ends, with a stopwatch and your own program. RV64GC settles one thing only: the binary gets through the door.